This invention relates to Very Large Scale Integrated (VLSI) microelectronic circuits and more particularly to a more efficient utilization of master slices in the production of such circuits.
The evolution of microelectronics has been discussed in many books and articles. For example, in the Scientific American book entitled "Microelectronics", published in 1977 by W. H. Freeman and Co. the book-publishing affiliate of Scientific American, a variety of individual articles address the nature of microelectronic elements, their design and fabrication particularly in the form of Large Scale Integrated Circuits, their applications, and their impact for the future.
The IBM Journal of Research and Development has had a number of articles from time to time concerning various microelectronics technologies of this nature which are included in the May 1981 issue: "VLSI Circuit Design", the May 1982 issue: "Packaging Technology" and the September 1982 issue: "Semiconductor Manufacturing Technology".
Complementary Metal Oxide Semiconductor (CMOS) technologies are of special interest in the present patent application. Other Metal Oxide Semiconductor (MOS) technologies are set forth in the Scientific American book. A number of other manufacturing techniques of basic interest are also described, in the Scientific American book. As one example, on page 42 thereof Large Scale Integrated circuits may be produced by computer control by proceeding through a number of steps including the use of optical techniques for generating topological patterns.
Other items of interest to microelectronics fabrication in particular, including master slice layout, logic cell layout and arrangements for achieving high density in such circuits include the following:
Technical Disclosure Bulletin article number PO 141,578 entitled "Cascode Decoder" by J. E. Gersbach and J. K. Shortle, published September 1965, Vol. 8, No. 4 at pp. 642-643 which concerns closely controlled input voltages, differentially connected to the inputs of a cascode decoder thereby providing high speed operation with minimum power dissipation.
Technical Disclosure Bulletin article number FI871-0895 entitled "Bipolar FET High-Speed Logic Switch" by R. D. Lane, published May 1972, Vol. 14, No. 12 at pp. 3684-3685 relating to the high speed operation of both positive and negative transitions at low power in a bipolar transistor current switch circuit by the provision of a pair of cross-connected field-effect transistor (FET) loads for the current switch bipolar transistors.
Technical Disclosure Bulletin article number MA877-0019 entitled "Merged Transistor Logic Cell for Logic Master Slice Layout" by H. R. Gates published March 1978, Vol. 20, No. 10 at p. 4013. This article relates to a logic cell layout which minimizes channel blocking for an integrated injection logic master slice array.
Technical Disclosure Bulletin article number GE878-0041 entitled "Integrated Logic Cell Array Layout" by K. Helwig published January 1980, Vol. 22, No. 8A, pp. 3258-3259 which concerns the density and/or wiring capabilities of a merged transistor logic (MTL) array that can be improved by placing MTL cells in the X and Y directions adjacent to a common injector region.
Technical Disclosure Bulletin article number FR876-0335 entitled "Generation of Mask Layout from Topological Equations" by B. Vergnieres published December 1980, Vol. 23, No. 7A, pp. 2833-2835 provides for the combination of manual design and automatic design automation which together provides the greatest flexibility, rapidity and density for manufactured integrated circuits.
Technical Disclosure Bulletin article number EN880-0261 entitled "Cascode Parity Circuit" by E. L. Carter and H. T. Ward published August 1981, Vol. 24, No. 3, pp. 1705-1706 providing for a customized cascode current switch circuit which facilitates parity generation with fewer logic stages than conventional circuits.
U.S. Pat. No. 3,233,223 to F. K. Buelow et al which provides for a high speed trigger having an output after a single transistor delay.
U.S. Pat. No. 3,446,989 to F. G. Allen et al having the provision of a multiple level integrated semiconductor logic circuit connected and operative to control a bistable element.
U.S. Pat. No. 3,475,621 to A. Weinberger relating to high-density integrated circuit arrangements for generating complex logical functions that include combinational and sequential logic.
U.S. Pat. No. 3,760,190 to C. W. Hannaford using a multiple input latching circuit which responds to the satisfaction of any one or more of a plurality of predetermined input signal conditions by the production of an output signal persisting, until reset, irrespective of any change in the input signals.
U.S. Pat. No. 3,978,329 to C. R. Baugh et al relating particularly to digital logic circuits for performing digital arithmetic functions.
U.S. Pat. No. 4,176,287 to J. J. Remedi concerns digital decoders for decoding digital signals and especially a CMOS decoder capable of providing one or more of n decoded outputs.
U.S. Pat. No. 4,249,193 to J. Balyoz et al concerning an improved masterslice design technique including structure, wiring and method of fabricating thereby providing improved Large Scale Integrated Devices.
U.S. Pat. No. 4,295,149 to J. Balyoz et al which utilizes improved LSI semiconductor design structures thereby enabling increased density and optimized performance of semiconductor devices, circuits and part number functions.
In the production of microelectronic circuitry heretofore a generalized approach has been the use of macro logic elements. In usual practice, the macro logic elements have been maintained in a library for access as needed for circuit production. Usually a number of the macro elements have been combined in order to produce a finished chip or logic product. The macro libraries have to be individually designed until a critical number of library entities are arrived at before a generalized logic machine can be efficiently implemented using them. The design of a full set might take many years to complete thus resulting in difficulty in designing an efficient desired finished product. Further, the physical images used during circuit production and derived from the macros referred to are further constrained as a result of the macro concepts.
The primary objective of the present invention is to overcome inherent limitations imposed heretofore due to use of macro concepts in DCVS circuit fabrication.